Cisco Optical Switch

There are 24x 10GE ports on the boards. No additional licenses are required to use FCoE and CEE, only hardware.

By tradition, only Brocade-branded SFP + can be used. FCoE, of course, travels only over short distances, while LR SFPs are only for network traffic. Copper twinax cables must not be used. They are only suitable for 8000 switches.

Type of optical cable

Maximum length

33 m (OM1) 82 m (OM2) 300 m (OM3) 380 m (OM4) 2.5 km (CEE traffic) 10 km (Ethernet traffic) From the point of view of internal architecture, FCOE10-24 can be considered as two integrated switches . ASIC Anvil is responsible for the transmission of CEE, and 8Gbps Condor2 for FC traffic. Both of them use the Cut-through switching method. The board is based on 3x Anvil chips. Each of them is responsible for a group of 8x TE ports (Ten gigabit Ethernet). The ASICs of all the boards in DCX are connected to each other and logically are a single switch that processes all Ethernet and CEE traffic. Anvil is also responsible for the operation of the FIP (FCoE Initialization Protocol) protocol and recognizing FCoE, redirects traffic to Zeus FPGAs. Zeus is used as an adapter for Anvil-Condor2 communication and provides encapsulation / decapsulation of FCoE frames. He is also responsible for providing the FPMA (Fabric Provided MAC Address) that is needed to correctly route FCoE frames on an Ethernet network. All FC traffic is handled by a single Condor2 ASIC. To represent FCoE ports in an FC factory, it creates virtual VF ports (Virtual Fabric Ports). To transfer data to the FC boards, the ASIC Condor2 is connected to the ASICs of both Core blades. Let’s look at the entire path of the frames. When the CEE port receives the FCoE frame, it addresses it to “its own” ASIC Anvil, which in turn redirects the data for decapsulation to Zeus. Next, the data is transmitted to Condor2. Each physical TE port can only have one virtual VE port (and vice versa). In the example in the figure, TE port 23 is mapped to VF port 23. After that, the data already travels through the FC protocol and, having passed the backplain, go to ASICs located on Core Blades.

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